I2C Specification & I2C Serial Bus Interface

Looking for a powerful I2C Analyzer for monitoring, decoding or debugging? Real-time data capture, decoding, filtering and display of I2C packets?

The I2C serial bus interface, introduced by Philips as a simple and inexpensive means of interfacing consumer electronics microchips, has become the de facto standard for equipment of various purposes. It is very practical for small data exchange applications (e.g., for configuring various devices). The I2C specification defines a two-way data transmission protocol over two signal lines. This protocol is used in a diverse range of applications, with the information content depending on the particular application. The ACCESS.Bus and SMBus are based on the I2C specification.

The Inter IC Bus, or I2C for short, is a synchronous serial bus providing bidirectional data transfer between connected devices. The bus is directed at 8-bit transfers. Data may be transmitted in both the one-address mode to a selected device and in the broadcast mode. Signal levels are standard, and compatible with the commonly used TTL, CMOS, and N-MOS logic of both the +5 V and +3.3 V (and lower) types. The protocol functions of the I2C microchips are usually supported by hardware. The protocol allows interaction on one bus between devices with different interface speeds. The requirements to the signal timing parameters are quite liberal; therefore, computers and microcontrollers without hardware support for the I2C bus can implement its protocol purely by software.

The I2C bus has been in use for a long time; the official Version 1.0 came out in 1992. The option to specify the address of the slave device by software that existed in the previous (draft) versions has been eliminated as too complicated and unused. The Low Speed mode, which is a special case of the Standard Mode (S) with a speed of 0-100 kbps, has also been eliminated. Version 1.0 introduced the definition of the Fast Mode (F), with a speed of 0-400 kbps and related changes in the requirements to the signal slope control and the interference filtration. The 10-bit device-addressing mode was also introduced in Version 1.0. Version 2.0 was introduced in 1998, when the I2C interface became the de facto standard of the industry, and used in a great number of different integrated circuits. In this version, a new High speed (Hs) mode appeared with transmission speeds of up to 3.4 Mbps. In terms of logic, the F and S modes function similarly and are designated by a common term, F/S. Version 2.0 revised the requirements for the level and shape of the signal, taking into account the high speeds and a possibility of connecting 2 V and lower devices. Version 2.1 (2000) clarified some points in the Hs mode timings. The information presented here is based on the specification for the Version 2.1 of the I2C bus.

The I2C interface uses 3 wires: GND and two signal lines - the SDA (Serial Data) line and the SCL (Serial Clock) line. Two devices are involved in the exchange process: a master and a slave. The master and the slave devices can play role of both the transmitter and receiver of data. The protocol allows presence of several master devices on the bus, and has a simple collision-detection and arbitration mechanism.

The exchange protocol for regular F/S devices is shown in the figure below. Both signal lines are connected to a positive power supply voltage via pull-up resistors. A device has an open-collector (open-drain) transmitter and a receiver connected to each line; the slave device does not have to have a transmitter on the SCL line. All transmitters with the same name are connected to the line, forming a wired-AND circuit: The line level will be high if all transmitters are inactive, and low if even one of the transmitters has its output transistor open. In the Idle state, all transmitters are inactive. The synchronization is set by the master device, but the slave device can slow down the data exchange if it cannot keep up with the transmission speed.

Transmissions are initiated by the master by generating the Start condition after it ascertains that the bus is available (i.e., when the SCL and SDA signals are high). The Start condition, represented by the s symbol on timing diagrams, is a high to low transition of the SDA signal while the SCL signal is high. The operation is completed by the Stop condition: a low to high transition of the SDA signal while the SCL signal is high. This condition is also always initiated by the master device. While the data are being transmitted, the SDA line can change its state only at the low SCL signal; data bits are considered valid during the high level SCL signal. The master device can begin the next transmission right after the current without generating the Stop condition; this is called repeated Start.

Each data transmission consists of 8 bits generated by the transmitter (the MSB is transmitted first). After transmitting each byte, the transmitter releases the line for one clock in order to receive the acknowledgment. During this ninth clock, the receiver generates the Ack acknowledge bit, which is used by the transmitter to ascertain that it has been "heard." After transmitting the Ack bit, the slave device may hold up the transmission of the next byte by holding the SCL line low. In the F/S modes, the slave device can delay bus transmissions at the bit level by holding the SCL signal low after the master releases it. Therefore, the master device must not generate the SCL signal haphazardly, but after first analyzing the SCL line: Having released this signal, it can generate a new one (opening the transmitter's key) only after ascertaining that it has returned into the inactive state (high level). Otherwise, the timing will get out of sync. The SCL signal may be held in the low state by another device that is trying to obtain bus control simultaneously. The SCL clocking signal does not necessarily have to be uniform: How long it is held low is determined by the maximum time that the slowest device engaged in the exchange decides to hold it, even if there is a conflict among the devices involved in the exchange. How long the SCL is held high is determined by the fastest of the conflicting master devices.

A bus collision (conflict) may arise when two or more devices, being ascertained that the bus is free, simultaneously, or almost simultaneously, initiate data exchange. They all control the SCL and SDA lines and watch them. If a device sending a 1 (high level) senses a 0 (low level) on the SDA line at the instant clock, it must admit that it has lost the arbitration and relinquish the SCL and SDA lines. (However, it may continue to control the SCL line until the current byte has been transmitted). The winning device will not even notice the losing contenders, and will continue working. The arbitration may terminate at any point during the transfer generated by the master device. Information transmitted by the device that has won the arbitration does not become corrupted (a pleasant difference from Ethernet network collisions). If the master device that loses the arbitration can also function as a slave, it must switch into the slave mode, because the conflict may be caused by the winning master device trying to address it.

The ACK acknowledge bit generated at the end of each received byte by the receiving device performs several functions. When the transmitter is the master device, the receiver (slave) must generate a logical zero ACK bit confirming successful reception of the immediate byte. A logical one ACK bit (not acknowledge) generated in response to the issued address means that the addressed slave device either is not present on the bus or that it is busy executing some real-time task. If a slave does not acknowledge a data byte, it means that it is busy. If the master device does not receive an acknowledge bit, it must generate the Stop condition to free the bus. When the master device acts as a receiver, it must generate a logical zero ACK bit after each byte it receives except for the last byte, when a logical one ACK bit is generated. This serves to inform the slave device that the transmission has been completed and that it must release the SDA and SCL lines now so that the master device can generate a P or Sr condition.

Sending a general call pursues one of two goals. These goals are defined in the second byte, whose least significant bit (bit 0) is called B. When B=0, devices that have accepted the general call must either reset (if the second byte holds 000001 10b) or not (if the second byte holds 00000 100b) and then read the programmable part of their hardware address. Device must ignore other values in the second byte. How the address is programmed depends on the device (it is stated in its data sheet). When B =1, the general call is used for broadcast data transmission. In this case, the master device generates its address (the same one that it responds when acting as a slave) in the higher seven bits of the second byte, and then sends the bytes that it needs to deliver to the unknown recipient. The receiver (as a rule, an intelligent device) must acknowledge each byte it receives, starting with the general call byte, followed by the master device address and then the data bytes.

Broadcast transmission can be resorted to, for example, by hardware keyboard controllers, which do not know to what address their asynchronous messages are to be sent. Another scheme also is possible: Upon powering up (or resetting), this device becomes a slave receiver, to which the master device (the system controller) will communicate the address of the information recipient for further targeted transmissions, in which this device itself will be the master.

Ten-bit addressing has solved the problem of the address shortage: whereas there are only 112 addresses available in the 7-bit addressing mode, taking into account reserved combinations, the 10-bit addressing mode makes further 1024 addresses available. Data transmission by a 10-bit addressing master device is simple: Bits [2:1] of the first byte after the s (Sr) carry the upper address bits with bit 0 (the RW indicator) set to 0; the second byte carries the lower eight address bits, while the following bytes are the transmitted data. The receiver acknowledges the received bytes in the usual way. Data receiving by a master device is somewhat more complex, because the RW indicator explicitly indicates the transmission direction change after the first byte, and the master device cannot now send the lower part of the address. To get around this stumbling block, the master device begins reception of a 10-bit address as a dummy transmission: It sends the 10-bit write indicator and the two address bits in the first byte, with the rest of the address sent in the second byte. The master device then generates the Sr condition and sends a 10-bit read indicator (RW = 1) with the two upper bits of the same address. After the slave transmitter receives the same two upper address bits as before the Sr, it responds with an acknowledgment and starts transmitting data to the master device. This process continues and terminates the same way as 7-bit addressing. Combination exchanges also are possible in which a master device executes an actual transmission to a 10-bit device, generates an Sr condition, and then reads the same device. Combination 7- and 10-bit accesses to different devices are also possible employing the Sr condition. Broadcasting using 10-bit addressing is the same as in 7-bit, except that the address of the master device is sent in two bytes (the lower eight address bits are sent instead of the first data byte).

The high-speed Hs mode makes it possible to exchange data at speeds of up to 3.4 Mbps; at this speed, Hs devices are compatible with fast and standard devices (F/S). In order to make exchanges at such high speeds possible, the output and input buffers of the microchips must switch into a special operating mode in which the sent and received signals have different characteristics. Signals of high-speed devices are designated as SDAH and SCLH; in combined systems, they must be separated from the SDA and SCL lines of regular devices by special bridges in order to work in the Hs mode, as the behavior of F/S devices at these speeds is unpredictable. Arbitration is not possible in the Hs mode as it is carried out at the F/S mode speed; neither is it possible to have synchronization at each bit (slave device delaying the transmission); the master device sets a rigid ratio of the low and high levels of the SCLH signal duration (2 to 1). The slave device can slow down the exchange only after the acknowledgment bits.